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5V/3.3V 2.5Gbps LIMITING POST AMPLIFIER WITH SIGNAL DETECT
FEATURES
s s s s s s s s s 3.3V and 5V power supply options Up to 2.5Gbps operation Low noise Chatter-fee signal detect (SD) generation Open collector TTL signal detect (SD) output TTL EN input Differential PECL inputs for data Single power supply Designed for use with Micrel-Synergy laser diode driver and controller s Available in a tiny (3mm) 10-pin MSOP
SY88943V
DESCRIPTION
The SY88943V limiting post amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 2.5Gbps. Signals as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88943V generates a chatter-free Signal Detect (SD) open collector TTL output. The SY88943V incorporates a programmable level detect function to identify when the input signal has been lost. The SD output will change from logic "HIGH" to logic "LOW" when input signal is smaller than the swing set by SDLVL. This information can be fed back to the EN input of the device to maintain stability under loss of signal condition. Using SDLVL pin, the sensitivity of the level detection can be adjusted. The SDLVL voltage can be set by connecting a resistor divider between VCC and VREF as shown in Figure 3. Figure 4, 5, 6, and 7 show the relationship between input level sensitivity and the voltage set on SDLVL. The SD output is a TTL open collector output that requires a pull-up resistor for proper operation, Figure 1.
VCC SY88943V SD 4.7k to 10k
PIN CONFIGURATION
EN 1 DIN 2 /DIN 3 VREF 4 SDLVL 5 MSOP K10-1
10 VCC 9 DOUT 8 /DOUT 7 SD 6 GND
Figure 1. SD Output with Desired Rise Time
APPLICATIONS
s s s s s s 1.25Gbps and 2.5Gbps ethernet 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel 622Mbps SONET Gigabit interface converter 2.5Gbps SDH/SONET 2.5Gbps proprietary links
BLOCK DIAGRAM
DIN /DIN
Limiting Amplifer ECL Buffer
DOUT /DOUT
Enable
VREF VCC GND
Level Detect
EN
SDLVL
SD
Rev.: B
Amendment: /0
1
Issue Date: August 2000
Micrel
SY88943V
PIN NAMES
Pin DIN /DIN SDLVL EN SD GND /DOUT DOUT VCC VREF Type Data Input Data Input Input TTL Input TTL Output (Open Collector) Ground PECL Output PECL Output Power Supply Output Function Data Input Inverting Data Input SD Level Set Output Enable (Active High) Signal Detect Ground Inverting Data Output Data Output Positive Power Supply Reference Voltage Output for SD Level Set (see Fig. 3)
GENERAL DESCRIPTION
General The SY88943V is an integrated limiting amplifier intended for high-frequency fiber-optic applications. The circuit connects to typical transimpedance amplifiers found within a fiber-optics link. The linear signal output from a transimpedance amplifier can contain significant amounts of noise, and may vary in amplitude over time. The SY88943V limiting amplifier quantizes the signal and outputs a voltage-limited waveform. The EN pin allows the user to disable the output signal without removing the input signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC DIN, /DIN DOUT, /DOUT EN SDLVL VREF TA Tstore Rating Power Supply Voltage Input Voltage Output Voltage (with 50 load) Input Voltage Input Voltage Output Voltage Operating Temperature Range Storage Temperature Range Value 0 to +7.0 0 to VCC VCC -2.5 to VCC +0.3 0 to VCC 0 to VCC VCC -2.0 to VCC -40 to +85 -55 to +125 Unit V V V V V V C C
NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.
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Micrel
SY88943V
DC ELECTRICAL CHARACTERISTICS
VCC = +5V 10%, RLOAD = 50 to VCC -2V
TA = -40C Symbol ICC IIL IIH VCMR Voffset SDLVL VOL IOH VOH VOL VREF IREF VIH VIL Parameter Power Supply Current(1) 5V 3.3V Min. -- -- -0.3(6) -- -- GND +2.0 -- VREF Level(2) -- -- Max. 40 40 -- 20(4) 100(5) VCC 100 VCC 0.5 100 TA = 0C Min. -- -- -0.3(6) -- -- GND +2.0 -- VREF -- -- Max. 40 40 -- 20(4) 100(5) VCC 100 VCC 0.5 100 Min. -- -- -0.3(6) -- -- GND +2.0 -- VREF -- -- TA = +25C Typ. 33 28 -- -- -- -- 17 -- -- -- Max. 40 40 -- 20(4) 100(5) VCC 100 VCC 0.5 100 TA = +85C Min. -- -- -0.3(6) -- -- GND +2.0 -- VREF -- -- Max. 45 45 -- 20(4) 100(5) VCC 100 VCC 0.5 100 Unit mA mA A V mV V V A mV mV V mA V V
EN Input LOW Current EN Input HIGH Current Common Mode Range Differential Output Offset SDLVL Level SD Output Low SD Output Leakage(3)
DOUT and /DOUT HIGH Output DOUT and /DOUT LOW Output Reference Supply VREF Output Current EN Input HIGH Voltage EN Input LOW Voltage
VCC -1085 VCC -880 VCC -1025 VCC -880 VCC -1025 VCC -955 VCC -880 VCC -1025 VCC -880 VCC -1830 VCC -1555 VCC -1810 VCC -1620 VCC -1810 VCC -1705 VCC -1620 VCC -1810 VCC- 1620 VCC -1.38 VCC -1.26 VCC -1.38 VCC -1.26 VCC -1.38 VCC -1.32 VCC -1.26 VCC -1.38 VCC -1.26
-0.8 2.0 --
0.5 -- 0.8
-0.8 2.0 --
0.5 -- 0.8
4. VIN = 2.7V 5. VIN = VCC 6. VIN = 0.5V
-0.8 2.0 --
-- -- --
0.5 -- 0.8
-0.8 2.0 --
0.5 -- 0.8
NOTES: 1. No output load 2. IOL = + 2mA 3. VOH = 5.5V
AC ELECTRICAL CHARACTERISTICS
VCC = +5V 10%, RLOAD = 50 to VCC -2V
TA = -40C Symbol PSRR VID VOD tONL tONH tOFFL VSR HYS tr, tf Parameter Power Supply(1) Rejection Ratio Input Voltage Range Differential Output Voltage Swing(2) SD Release Time(3) Minimum Input SD Release Time(4) Maximum Input SD Assert Time(3) SD Sensitivity Range SD Hysteresis Output Rise/Fall Time Min. -- 5 -- -- -- -- -- 5 2 -- -- Max. -- 1800 -- -- 0.5 0.5 0.5 50 8 175 -- TA = 0C Min. -- 5 -- -- -- -- -- 5 2 -- -- Max. -- 1800 -- -- 0.5 0.5 0.5 50 8 175 -- -- 5 -- -- -- -- -- 5 2 -- -- TA = +25C Min. Typ. 35 -- 700 300 0.2 0.2 0.1 -- 4.6 150 trin,tfin Max. -- 1800 -- -- 0.5 0.5 0.5 50 8 175 -- TA = +85C Min. -- 5 -- -- -- -- -- 5 2 -- -- Max. -- Unit dB Conditions Input referred, 55MHz
1800 mVp-p -- -- 0.5 0.5 0.5 50 8 175 -- mV mV s s s MVp-p dB ps 223-1 pattern 223-1 pattern VID > 100mVp-p VID < 100mVp-p VID = 15mVp-p VID = 5mVp-p
NOTES: 1. Input referred noise = RMS output noise/low frequency gain. 2. Input is a 622MHz square wave.
3. Input is a 200MHz square wave, tr < 300ps, 8mVp-p. 4. Input is a 200MHz square wave, tr < 300ps, 1.8Vp-p.
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Micrel
SY88943V
DESIGN PROCEDURE
Output Termination The SY88943V outputs must be terminated with a 50 load to VCC -2V (or Thevenin equivalent). Layout and PCB Design Since the SY88943V is a high-frequency component, performance can be largely determined by the board layout and design. A common problem with high-gain amplifiers is the feedback from the large swing outputs to the input via the power supply. The SY88943V ground pin should be connected to the circuit board ground. Use multiple PCB vias close to the part to connect to ground. Avoid long, inductive runs which can degrade performance.
VCC
0.1F 0.1F DIN+
R1
DIN- 50 VREF 0.1F
SDLVL R2 VREF
50
Figure 2. Differential Input Configuration
Figure 3. SDLVL Circuit NOTES: R2 x 1.32V SDLVL = VCC -1.32V + R1 + R2 R1 + R2 2.6k
PRODUCT ORDERING CODE
Ordering Code SY88943VKC SY88943VKCTR Package Type K10-1 K10-1 Operating Range Commercial Commercial
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Micrel
SY88943V
PERFORMANCE CURVE
SD Assert and Deassert Levels vs SDLVL
100
SD Assert and Deassert Levels vs SD
LVL 100 90 80 70 60 50 40 30 20 10 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC- V (V) 5.0V TA = 25C 2.5Gbps Pattern 223-1
INPUT LEVEL (mVp-p)
70 60 50 40 30 20 10 0 0
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC- V (V)
Figure 4.
INPUT LEVEL (mVp-p)
90 80
3.3V TA = 25C 2.5Gbps Pattern 223-1
Figure 5.
SD Assert and Deassert Levels vs SD
LVL 100 90 80 70 60 50 40 30 20 10 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC- V (V) 3.3V TA = 25C 2.5Gbps Pattern 27-1
SD Assert and Deassert Levels vs SDLVL
100
INPUT LEVEL (mVp-p)
INPUT LEVEL (mVp-p)
90 80 70 60 50 40 30 20 10 0 0
5.0V TA = 25C 2.5Gbps Pattern 27-1
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2 SDLVL = VCC- V (V)
Figure 6.
Figure 7.
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Micrel
SY88943V
10 LEAD MSOP (K10-1)
Rev. 00
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Micrel
SY88943V
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Micrel
SY88943V
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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